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Bachelor's degree in Electrical Engineering or equivalent practical experience.
4 years of experience with verification methodology such as universal verification methodology (UVM).
2 years of experience in the verification of intellectual property (IP) designs such as IP, system on a chip (SoC), vector CPUs, etc.
Experience with verification methodologies and languages such as UVM or SystemVerilog.
Experience developing and maintaining verification testbenches, test cases, and test environments.

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Bachelor's degree in Electrical Engineering or equivalent practical experience.
4 years of experience with verification methodology such as universal verification methodology (UVM).
2 years of experience in the verification of intellectual property (IP) designs such as IP, system on a chip (SoC), vector CPUs, etc.
Experience with verification methodologies and languages such as UVM or SystemVerilog.
Experience developing and maintaining verification testbenches, test cases, and test environments.

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Bachelor's degree in Electrical Engineering or equivalent practical experience.
4 years of experience with verification methodology such as universal verification methodology (UVM).
2 years of experience in the verification of intellectual property (IP) designs such as IP, system on a chip (SoC), vector CPUs, etc.
Experience with verification methodologies and languages such as UVM or SystemVerilog.
Experience developing and maintaining verification testbenches, test cases, and test environments.

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