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Bachelor's degree in Electrical Engineering, or a related field, or equivalent practical experience.
4 years of experience in DFT specification definition architecture and insertion.
Experience with Application-Specific Integrated Circuit (ASIC) DFT synthesis, Static Timing Analysis (STA), simulation, and verification flow.
Experience in silicon bring-up, debug, and validation of DFT features on ATE, debugging Automatic Test Pattern Generation (ATPG) patterns, compressed ATPG patterns, Memory Built-In Self-Test (MBIST) and Joint Test Action Group (JTAG) related issues.
Experience with scan insertion, ATPG, gate level simulations and silicon debug, low power designs, BIST, JTAG, IJTAG tools and flow.

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Bachelor's degree in Electrical Engineering, or a related field, or equivalent practical experience.
4 years of experience in DFT specification definition architecture and insertion.
Experience with Application-Specific Integrated Circuit (ASIC) DFT synthesis, Static Timing Analysis (STA), simulation, and verification flow.
Experience in silicon bring-up, debug, and validation of DFT features on ATE, debugging Automatic Test Pattern Generation (ATPG) patterns, compressed ATPG patterns, Memory Built-In Self-Test (MBIST) and Joint Test Action Group (JTAG) related issues.
Experience with scan insertion, ATPG, gate level simulations and silicon debug, low power designs, BIST, JTAG, IJTAG tools and flow.

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Bachelor's degree in Electrical Engineering, or a related field, or equivalent practical experience.
4 years of experience in DFT specification definition architecture and insertion.
Experience with Application-Specific Integrated Circuit (ASIC) DFT synthesis, Static Timing Analysis (STA), simulation, and verification flow.
Experience in silicon bring-up, debug, and validation of DFT features on ATE, debugging Automatic Test Pattern Generation (ATPG) patterns, compressed ATPG patterns, Memory Built-In Self-Test (MBIST) and Joint Test Action Group (JTAG) related issues.
Experience with scan insertion, ATPG, gate level simulations and silicon debug, low power designs, BIST, JTAG, IJTAG tools and flow.

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