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Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
4 years of experience in the DFT , including implementation and DFT verification for the ASIC/SoC designs.
Experience in DFT validation, including Phase-Locked Loop (PLL), sensors, Gate Level Simulations (GLS) simulation with timing, generating test cases, and debugging GLS.
Experience in IEEE1149/1500/1687, CTL generation, MBIST, HSIOs, scan, Analog IPs, and Automatic Test Pattern Generation (ATPG).
Experience with industry-standard DFT EDA tools.

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Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
4 years of experience in the DFT , including implementation and DFT verification for the ASIC/SoC designs.
Experience in DFT validation, including Phase-Locked Loop (PLL), sensors, Gate Level Simulations (GLS) simulation with timing, generating test cases, and debugging GLS.
Experience in IEEE1149/1500/1687, CTL generation, MBIST, HSIOs, scan, Analog IPs, and Automatic Test Pattern Generation (ATPG).
Experience with industry-standard DFT EDA tools.

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Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
4 years of experience in the DFT , including implementation and DFT verification for the ASIC/SoC designs.
Experience in DFT validation, including Phase-Locked Loop (PLL), sensors, Gate Level Simulations (GLS) simulation with timing, generating test cases, and debugging GLS.
Experience in IEEE1149/1500/1687, CTL generation, MBIST, HSIOs, scan, Analog IPs, and Automatic Test Pattern Generation (ATPG).
Experience with industry-standard DFT EDA tools.

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