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Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
10 years of experience with Unified Power Format (UPF) and low-power verification methodologies, including power domain integration.
Experience with gate-level simulation and power aware GLS, including Standard Delay Format (SDF) timing annotation and X-propagation debug.
Experience in developing custom tools/scripts (Python/Perl/Tcl) to solve verification bottlenecks in the power-aware domain.
Experience in SoC architectures, power management controllers, and cross-domain reset/clock sequencing.

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Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
10 years of experience with Unified Power Format (UPF) and low-power verification methodologies, including power domain integration.
Experience with gate-level simulation and power aware GLS, including Standard Delay Format (SDF) timing annotation and X-propagation debug.
Experience in developing custom tools/scripts (Python/Perl/Tcl) to solve verification bottlenecks in the power-aware domain.
Experience in SoC architectures, power management controllers, and cross-domain reset/clock sequencing.

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Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
10 years of experience with Unified Power Format (UPF) and low-power verification methodologies, including power domain integration.
Experience with gate-level simulation and power aware GLS, including Standard Delay Format (SDF) timing annotation and X-propagation debug.
Experience in developing custom tools/scripts (Python/Perl/Tcl) to solve verification bottlenecks in the power-aware domain.
Experience in SoC architectures, power management controllers, and cross-domain reset/clock sequencing.

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