1a:[["$","title","0",{"children":"Silicon DFT Engineer, Cloud Silicon at Google | Software Jobs 4 Me | SoftwareJobs4Me"}],["$","meta","1",{"name":"description","content":"

Bachelor's degree in Electrical Engineering, or a related field, or equivalent practical experience.
4 years of experience in DFT specification definition architecture and insertion.
Experience with Application-Specific Integrated Circuit (ASIC) DFT synthesis, Static Timing Analysis (STA), simulation, and verification flow.
Experience in silicon bring-up, debug, and validation of DFT features on ATE, debugging Automatic Test Pattern Generation (ATPG) patterns, compressed ATPG patterns, Memory Built-In Self-Test (MBIST) and Joint Test Action Group (JTAG) related issues.
Experience with scan insertion, ATPG, gate level simulations and silicon debug, low power designs, BIST, JTAG, IJTAG tools and flow.

"}],["$","meta","2",{"name":"application-name","content":"SoftwareJobs4Me"}],["$","link","3",{"rel":"author","href":"https://softwarejobs4me.in"}],["$","meta","4",{"name":"author","content":"SoftwareJobs4Me"}],["$","meta","5",{"name":"keywords","content":"Silicon DFT Engineer, Cloud Silicon,Google,Bengaluru,software jobs,tech jobs,developer jobs,IT jobs,software engineer"}],["$","meta","6",{"name":"creator","content":"SoftwareJobs4Me"}],["$","meta","7",{"name":"publisher","content":"SoftwareJobs4Me"}],["$","meta","8",{"name":"robots","content":"index, follow"}],["$","meta","9",{"name":"googlebot","content":"index, follow, max-video-preview:-1, max-image-preview:large, max-snippet:-1"}],["$","meta","10",{"name":"category","content":"technology"}],["$","link","11",{"rel":"canonical","href":"https://softwarejobs4me.in/jobs/Info/google_131248234910622406"}],["$","meta","12",{"property":"og:title","content":"Silicon DFT Engineer, Cloud Silicon at Google | Software Jobs 4 Me"}],["$","meta","13",{"property":"og:description","content":"

Bachelor's degree in Electrical Engineering, or a related field, or equivalent practical experience.
4 years of experience in DFT specification definition architecture and insertion.
Experience with Application-Specific Integrated Circuit (ASIC) DFT synthesis, Static Timing Analysis (STA), simulation, and verification flow.
Experience in silicon bring-up, debug, and validation of DFT features on ATE, debugging Automatic Test Pattern Generation (ATPG) patterns, compressed ATPG patterns, Memory Built-In Self-Test (MBIST) and Joint Test Action Group (JTAG) related issues.
Experience with scan insertion, ATPG, gate level simulations and silicon debug, low power designs, BIST, JTAG, IJTAG tools and flow.

"}],["$","meta","14",{"property":"og:url","content":"https://softwarejobs4me.in/jobs/Info/google_131248234910622406"}],["$","meta","15",{"property":"og:site_name","content":"Software Jobs 4 Me"}],["$","meta","16",{"property":"og:image","content":"https://examsolver-fe.s3.ap-south-1.amazonaws.com/company_logos/google.png"}],["$","meta","17",{"property":"og:image:width","content":"1200"}],["$","meta","18",{"property":"og:image:height","content":"630"}],["$","meta","19",{"property":"og:image:alt","content":"Google Logo"}],["$","meta","20",{"property":"og:type","content":"website"}],["$","meta","21",{"name":"twitter:card","content":"summary_large_image"}],["$","meta","22",{"name":"twitter:title","content":"Silicon DFT Engineer, Cloud Silicon at Google | Software Jobs 4 Me"}],["$","meta","23",{"name":"twitter:description","content":"

Bachelor's degree in Electrical Engineering, or a related field, or equivalent practical experience.
4 years of experience in DFT specification definition architecture and insertion.
Experience with Application-Specific Integrated Circuit (ASIC) DFT synthesis, Static Timing Analysis (STA), simulation, and verification flow.
Experience in silicon bring-up, debug, and validation of DFT features on ATE, debugging Automatic Test Pattern Generation (ATPG) patterns, compressed ATPG patterns, Memory Built-In Self-Test (MBIST) and Joint Test Action Group (JTAG) related issues.
Experience with scan insertion, ATPG, gate level simulations and silicon debug, low power designs, BIST, JTAG, IJTAG tools and flow.

"}],"$L1c","$L1d","$L1e","$L1f"]