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Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of professional experience in ASIC/SoC digital design using SystemVerilog.
Experience working on multi-stage, high-performance CPU pipelines and optimizing them for area, power, and timing.
Experience in logic design through coursework or industry experience.
Experience with RISC-V architecture and ISA extensions.
Experience with micro-architecture and RTL design experience in one CPU pipeline stage (e.g., Instruction Fetch Unit (IFU), Decode/Issue/Execution units, or Load-Store Unit (LSU)).

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Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of professional experience in ASIC/SoC digital design using SystemVerilog.
Experience working on multi-stage, high-performance CPU pipelines and optimizing them for area, power, and timing.
Experience in logic design through coursework or industry experience.
Experience with RISC-V architecture and ISA extensions.
Experience with micro-architecture and RTL design experience in one CPU pipeline stage (e.g., Instruction Fetch Unit (IFU), Decode/Issue/Execution units, or Load-Store Unit (LSU)).

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Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of professional experience in ASIC/SoC digital design using SystemVerilog.
Experience working on multi-stage, high-performance CPU pipelines and optimizing them for area, power, and timing.
Experience in logic design through coursework or industry experience.
Experience with RISC-V architecture and ISA extensions.
Experience with micro-architecture and RTL design experience in one CPU pipeline stage (e.g., Instruction Fetch Unit (IFU), Decode/Issue/Execution units, or Load-Store Unit (LSU)).

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