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\nMaster's degree in Electrical Engineering, Physics, Computer Engineering, Materials Science or related field or equivalent practical experience.
4 years of experience in the SOC design/verification.
Experience verifying digital logic at the Register Transfer Level (RTL) using SystemVerilog at Subsystem or Full chip level.
Experience in mobile SOC performance model development, performance analysis, and workload characterization.

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\nMaster's degree in Electrical Engineering, Physics, Computer Engineering, Materials Science or related field or equivalent practical experience.
4 years of experience in the SOC design/verification.
Experience verifying digital logic at the Register Transfer Level (RTL) using SystemVerilog at Subsystem or Full chip level.
Experience in mobile SOC performance model development, performance analysis, and workload characterization.

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\nMaster's degree in Electrical Engineering, Physics, Computer Engineering, Materials Science or related field or equivalent practical experience.
4 years of experience in the SOC design/verification.
Experience verifying digital logic at the Register Transfer Level (RTL) using SystemVerilog at Subsystem or Full chip level.
Experience in mobile SOC performance model development, performance analysis, and workload characterization.

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