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Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization.
Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions.
Knowledge in timing convergence of high frequency data-path intensive Cores and advanced STA concepts
Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes
Good understanding of clocking architecture.
Should be able work in close collaboration with"}],["$","meta","2",{"name":"application-name","content":"SoftwareJobs4Me"}],["$","link","3",{"rel":"author","href":"https://softwarejobs4me.in"}],["$","meta","4",{"name":"author","content":"SoftwareJobs4Me"}],["$","meta","5",{"name":"keywords","content":"Physical Design - Sr Engineer,Qualcomm,Chennai, TN, IN,software jobs,tech jobs,developer jobs,IT jobs,software engineer"}],["$","meta","6",{"name":"creator","content":"SoftwareJobs4Me"}],["$","meta","7",{"name":"publisher","content":"SoftwareJobs4Me"}],["$","meta","8",{"name":"robots","content":"index, follow"}],["$","meta","9",{"name":"googlebot","content":"index, follow, max-video-preview:-1, max-image-preview:large, max-snippet:-1"}],["$","meta","10",{"name":"category","content":"technology"}],["$","link","11",{"rel":"canonical","href":"https://softwarejobs4me.in/jobs/Info/qualcomm_446717841315"}],["$","meta","12",{"property":"og:title","content":"Physical Design - Sr Engineer at Qualcomm | Software Jobs 4 Me"}],["$","meta","13",{"property":"og:description","content":"

Company:
Qualcomm India Private Limited
Job Area:
Engineering Group, Engineering Group > Hardware Engineering
General Summary:
- Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization.
- Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions.
- Knowledge in timing convergence of high frequency data-path intensive Cores and advanced STA concepts
- Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes
- Good understanding of clocking architecture.
- Should be able work in close collaboration with"}],["$","meta","14",{"property":"og:url","content":"https://softwarejobs4me.in/jobs/Info/qualcomm_446717841315"}],["$","meta","15",{"property":"og:site_name","content":"Software Jobs 4 Me"}],["$","meta","16",{"property":"og:image","content":"https://examsolver-fe.s3.ap-south-1.amazonaws.com/company_logos/qualcomm.png"}],["$","meta","17",{"property":"og:image:width","content":"1200"}],["$","meta","18",{"property":"og:image:height","content":"630"}],"$L10","$L11","$L12","$L13","$L14","$L15","$L16","$L17","$L18"]